Matrix and pipeline mirror-symmetrical adders
Let's consider the matrix multi-digit ternary mirror-symmetrical adder (Fig. 1).
Each cell of the matrix adder in Fig. 1 is the ternary mirror-symmetrical single-digit full adder having 4 inputs and 2 outputs. The matrix adder in Fig. 1 consists of the 21 single-digit full adders arranged in the form of the 7 ´ 3-matrix. Each ternary single-digit adder has a designation of where the number 4 means that the adder has 4 ternary inputs, the lower index The inputs of the single-digit adders of the first row form the multi-digit input of the matrix ternary mirror-symmetrical adder. The output of the intermediate sum of each single-digit adder is connected to the corresponding input of the next single-digit adder of the same column. The outputs of the intermediate sum of the single-digit adders of the last row form the multi-digit output of the matrix ternary mirror-symmetrical adder. The basic peculiarity of the matrix mirror-symmetrical adder in Fig. 1 consists of the special organization of the connections between the carry outputs of the single-digit adders and the inputs of the neighboring single-digit adders. The carry outputs of all the single-digit adders with the even low indices (2, 0, -2) are connected to the corresponding inputs of the neighboring single-digit adders aligned in the same row but the carry outputs of all the single-digit adders with the odd low indices (3, 1, -1, -3) are connected to the corresponding inputs of the neighboring single-digit adders aligned in the low row. Note that such organization of carry connections allows eliminating the above-considered "swing" phenomenon. Let's consider operating the matrix mirror-symmetrical adder for the concrete example. Let's sum up two equal mirror-symmetrical numbers:
The addition consists of 2 stages. Each of the stages is realized by one row of the single-digit adders and consists of two steps.
Hence the first step is the formation of the intermediate sums and the carries on the outputs of the single-digit adders of the first row with the even low indices (2, 0, -2). At the second step the single-digit adders with the odd low indices (3, 1, -1, -3) enter into action. Taking into consideration the carries entered from the neighboring single-digit adders of the same row they form the intermediate sums and the carries entering the single-digit adders of the low row, i.e. The first stage is over. We can see that some intermediate sums and some carries entering the adders of the lower row are the results of the first stage. These intermediate sums and carries contain in themselves full information about the summable numbers.
AS all the carries formed at this stage became equal to 0 this means that the addition is over at the second stage (this is true only for the case considered). The obtained sum enters the inputs of the lower row adders and then appears on the output of the adder.
Thus we have considered the highly unusual mirror-symmetrical arithmetical device allowing to perform in the pipeline regime three important arithmetical operations: addition, subtraction and multiplication of the mirror-symmetrical numbers. But if integers are the input information of the mirror-symmetrical adder in this case the output information will be represented in the mirror-symmetrical form. This means that the mirror-symmetrical numbers allows controlling the arithmetical processes in it. We can realize the pipeline mirror-symmetrical adder only for the case if we use the ternary registers in it. But what means the "ternary register". We will give an answer this question at the next page of our Museum. Follow us! |